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posted by  zenmas on 7/25/2008 12:59:35 AM  |  status: Live  

Computer Operating Systems

Course Textbook Chapter Problem
Operating Systems Operating System Concepts (7th) by Silberschatz, Galvin, Gagne N/A N/A
Question Details:
Can someone please help me?
Consider a CPU with a TLB that caches 512 page table entries. A mapped memory access (during a TLB hit) takes 1200 ps. One access to main memory takes 1000 ps. What are the TLB access time and the TLB hit rate such that the effective memory-access time is 1250 ps ?

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posted by sam_GT on 7/25/2008 2:20:09 AM  |  status: Live
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zenmas's comment:
"thank you thank you"
Response Details:

Here,

TLB access time = (TLB+ Memory )access time - Memory Access time
                           =1200 - 1000 = 200ps.

Effective access time = hit_ratio * (Time_access_during_hit) + (1 - hit_ratio ) * ( Memory_access_Time + Time_access_during_hit)

1250 = hit_ratio * 1200 +  (1 - hit_ratio) (1200 + 1000)
1250 = hit_ratio * 1200 +  (1 - hit_ratio) (3200 )
hit_ratio * 2000 = 3200 -1250
hit_ratio =  .975
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