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Date Posted: 1/5/2008 12:09:51 AM  Status: Live
cs 401
Course Textbook Chapter Problem
Computer Architecture N/A N/A N/A
Question Details:
 

Give answers to each.

a.       How can we hook an interrupt?

b.      How the address of a required interrupt handler is found?

c.       What is difference between maskable and non-maskable interrupts?

d.      Briefly explain the context switching with example.

e.       When an IRET instruction is executed, what action takes place?

Answers:

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Date Posted: 1/5/2008 3:27:07 AM  Status: Live
Asker's Rating: Helpful   
Response:
Solution (a):
        Interrupts can occur when the processor is either in real mode (like when your program calls some DOS service) or in protected mode. When your program runs under a DPMI host, hardware interrupts are caught by the DPMI host and passed to protected mode first; only if unhandled, they are then reflected to real mode. Therefore, in DPMI mode you can get away with installing only a protected-mode handler. However, if the interrupts happen at a high frequency (say, more than 10 KHz), and if your program spends lots of time calling real-mode DOS/BIOS functions, then the overhead of the interrupt reflection from real to protected mode might be too painful, and you should consider installing a real-mode interrupt handler in addition to the protected-mode one. Such a real-mode handler will be called before the interrupt gets to the DPMI host, and handle the interrupt entirely in real mode, so it must be written in assembly and located in conventional memory (below the 1MB mark). If you need to hook an interrupt with both PM and RM handlers, you must hook the PM interrupt first, then the RM one (because hooking the PM interrupt modifies the RM one).
 
Solution (b):
       Means for registering an instruction address breakpoint interrupt handler with said kernel, wherein said instruction address breakpoint interrupt handler is within said kernel extension;
 
Solution (c):
Maskable Interrupts: A maskable interrupt (IRQ) is a hardware interrupt that may be ignored by setting a bit in an interrupt mask register's (IMR) bit-mask.
    
Non-Maskable Interrupts: All of the regular interrupts that we normally use and refer to by number are called maskable interrupts. The process is able to mask, or temporarily ignore, any interrupt if it needs to, in order to finish something else that it is doing. In addition, however, the PC has a non-maskable interrupt (NMI) that can be used for serious conditions that demand the processor's immediate attention. The NMI cannot be ignored by the system unless it is shut off specifically.
 
Solution (d):
      A context switch can mean a register context switch, a task context switch, a thread context switch, or a process context switch. What constitutes the context is determined by the processor and the operating system
Example:
-- Switch execution context to the adventure-works\dan1 login account.
EXECUTE AS LOGIN = 'adventure-works\dan1';
-- Create the new login account.
CREATE LOGIN Jinghao1 WITH PASSWORD = '3KHJ6dhx(0xVYsdf';
-- Revert to the previous execution context.
REVERT;
 
Solution (e):
The Interrupt-In-Service-Flag is set at the beginning of an interrupt-acknowledge cycle. It is reset by the IRET (Interrupt-RETurn) instruction. When IIS is set, interrupts are disabled. When the Status-register is read, IIS always reads as '0'.

 
Plz Dont Forget to Rate my Answer :)
cs 304's Comment:
help ful gud.

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Date Posted: 1/5/2008 7:06:48 AM  Status: Live
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Response:

Part(a):

To hook an interrupt we change the vector corresponding to that interrupt. As soon as the interrupt vector changes, that interrupt will be routed to the new handler. So introducing a new entry in the mapping table is called hooking an interrupt.

Part(b):
The correlation process from the interrupt number to the interrupt handler uses a table called interrupt vector table. Its location is fixed to physical memory address zero. Each entry of the table is four bytes long containing the segment and offset of the interrupt routine for the corresponding interrupt number. The first two bytes in the entry contain the offset and the next two bytes contain the segment. Mathematically offset of the interrupt n will be at nx4 while the segment will be at nx4+2. One entry in this table is called a vector.

Part(c):
The processor can inhibit certain types of interrupts by use of a special interrupt mask bit. This mask bit is part of the condition code register, or a special interrupt register. If this bit is set, and an interrupt request occurs on the interrupt request input, it is ignored. There are some interrupts which cannot be masked out or ignored by the processor. These are associated with high priority tasks which cannot be ignored (like memory parity or bus faults). In general, most processors support the Non-Maskable Interrupt (NMI). This interrupt has absolute priority, and when it occurs, the processor will finish the current memory cycle, and then branch to a special routine written to handle the interrupt request.

Part(d):
A context switching involves storing the old state and retrieving the new state. When the interrupt instruction is called, the values of CS, IP and Flags are stored on the stack and these values are restored at the end of servicing the current interrupt.

Part(e):
The values of CS, IP and Flags are popped from stack.

Dont forget to rate my answer

cs 304's Comment:
gudddddddddddddd!

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